1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Related Art Statements
A scale or circuit structure of integrated semiconductor devices has become larger and larger in order to satisfy a requirement of large capacity and large variety of performances. This results in a miniaturization of elements and a design rule has become smaller and smaller such as half microns and quarter microns. In order to reduce a size of elements, it is also required to miniaturize an isolation region for isolating adjacent elements from each other.
As a technique for isolating adjacent elements from each other, there has been developed a method of isolating the elements by dielectric material, and this method has been practiced by a local oxidation technique called LOCOS.
FIGS. 1a to 1e are schematic cross sectional views showing successive steps of a method of manufacturing C-MOS FET in accordance with a known LOCOS. At first, as shown in FIG. 1a, on a surface of a P-type silicon substrate 11 is formed a silicon oxide film 12 having a thickness of about 1500 .ANG.. Then, after selectively implanting N type impurity ions, they are driven into the silicon substrate 11 by heating it at 1150.degree. C. for about ten hours to form an N-type well 13 as illustrated in FIG. 1b. Then, a silicon oxide film 12a of a thickness of about 350 .ANG. is formed, said silicon oxide film serving as a pad layer for a silicon nitride to be formed later.
Next, a silicon nitride film having a thickness of 1500 .ANG. is uniformly formed on the silicon oxide film and then is patterned into a desired anti-oxidation film 14, and P-type impurity ions, i.e. channel stopper ions are implanted as depicted in FIG. 1c. These P-type impury ions serve to prevent the inversion of channel of an N-type FET. Thereafter, a thermal oxidation treatment is performed at a temperature of about 1000.degree. C. to form locally field oxide films 12b having a thickness of about 6000 .ANG. as shown in FIG. 1d. After removing the silicon oxide film 12a by etching, a gate oxide film 12c of a thickness of about 200 .ANG. is newly formed. During the formation of the field oxide film 12b, channel stopper regions 15 are also formed.
Next, a poly silicon film having a thickness of about 4000 .ANG. is uniformly deposited and a large amount of N-type impurity ions are doped therein by PoCl.sub.3 at 900.degree. C. Then, the poly silicon film is selectively patterned to form gate electrode 16 as illustrated in FIG. 1e. Next, a resist 17 is applied on a portion of the substrate above the N-type well 13 in which an P-type FET is to be formed, and N-type impurity ions are implanted into a portion of the substrate 11 at which an N-type FET is to be formed later as depicted in FIG. 1f.
After removing the resist 17, a silicon oxide film having a thickness of about 2000 .ANG. is formed by CVD method, and an anisotropic etching is carried out to form side walls 18 on side surfaces of the gate electrodes 16 made of poly silicon as shown in FIG. 1g. By this process, low impurity density regions 19 and 20 of source and drain of N-type FET are formed.
Next, a portion of the substrate at which the N-type FET is to be formed is covered with a resist 21, P-type impurity ions are implanted at a high density for constructing source and drain of the P-type FET as shown in FIG. 1h.
After removing the resist 21, a region of the P-type FET is covered with a new resist, and N-type impurity ions are implanted at a high density in order to form highly doped regions for source and drain of the N-type FET. Then, implanted P-type and N-type impurity ions are driven into the substrate 11 to form highly doped source and drain regions 22 and 23 for N-type FET. At the same time, source and drain regions 24 and 25 of the P-type PET are formed. Thereafter, a passivation film 26 made of CVD-SiO.sub.2 and BFSG (borophosphosilicate glass) is provided by deposition and then is reflowed by heating the substrate in an atmosphere of nitrogen at 900.degree. C. as depicted in FIG. 1i.
Next, contact holes 27 are formed in the passivation film 26 as shown in FIG. 1j and a metal film having a thickness of about 1.0 .mu.m is deposited and is patterned to form metal wiring 28 as illustrated in FIG. 1k. Finally, a plasma nitrogen film 29 having a thickness of about 1.0 .mu.m is formed as a passivation film, and then an alloying process is carried out to manufacture C-MOS FETs as shown in FIG. 1e.
As stated above, in recently developed semiconductor devices, transistors are required to have very high performances, so that they are miniaturized and density is increased. At the same time, a diffusion depth has becomes shallower such as 0.1 to 0.2 .mu.m. Further a gate width which relates to a switching speed has become narrower year after year and a size of a single transistor has become extremely small.
However, the above requirements could not be fully satisfied due to various reasons. One of these problems is a bird's beak which is produced during the selective oxidation for forming the field oxide film. The bird's beak is produced by a lateral diffusion of oxygen along the silicon oxide film which is formed between the silicon substrate and the silicon nitride film and serves as a pad or buffer for preventing the generation of crystal defects. Therefore, the bird's beak is related to a thickness of the buffer silicon oxide film and an oxidation temperature. In "Laterally Sealed LOCOS Isolation" in "JOURNAL OF THE ELECTROCHEMICAL SOCIETY", June 1987, pp.1475 to 1479, there is described a method of mitigating the generation of the bird's beak. Then, this method will be explained with reference to FIGS. 2a to 2c.
FIGS. 2a to 2c are schematic cross sectional views illustrating successive steps of the above mentioned known method of suppressing the generation of the bird's beak. On a silicon substrate 31 there are successively formed a buffer silicon oxide film 32, an anti-oxidation silicon nitride film 33 and a silicon oxide film 34. After etching these films selectively into a given pattern, a silicon nitride film 35 is formed over a whole surface as shown in FIG. 2a.
Next, a spacer 36 made of silicon nitride is formed on a side wall of these films 32, 33, 34 by effecting an anisotropic etching. Then, the silicon oxide film 34 within the spacer 36 is selectively removed by etching as illustrated in FIG. 2b.
Then, isolation regions 37 are formed by a local oxidation as depicted in FIG. 2c. In this case, the spacer 36 made of silicon nitride film is directly contacted with the bulk of the silicon substrate 31, and thus during the field oxidation, an oxygen introduction path is suppressed by the spacer 36. In this manner, the generation of the bird's beak can be mitigated by suitably designing the structure.
In the known method of preventing the generation of the bird's beak, the spacer 36 is directly contacted with the silicon substrate 31 in order to reduce the passage of the oxygen. However, expansion coefficients of the silicon substrate and spacer are different from each other, and thus there is produced a stress. This results in crystal defects in the silicon substrate after the local oxidation and a leak current between elements is liable to be increased. In a memory device such as S-RAM, a standby leak current is increased.
In the local oxidation disclosed in the above reference, in order to reduce the lateral passage of oxygen by suitably designing the construction, an assembly of SiO.sub.2 --Si.sub.3 N.sub.4 --SiO.sub.2 films is etched into a desired pattern to expose a surface of the bulk of the silicon substrate 31 and the silicon nitride film 35 is deposited thereon as shown in FIG. 2a, and then the spacer 36 is formed by the anisotropic reactive ion etching.
The spacer 36 is formed on a side wall of the above mentioned assembly of SiO.sub.2 --Si.sub.3 N.sub.4 --SiO.sub.2 films and is subjected to a stress. Further, the spacer 36 is directly contacted with the bulk of the silicon substrate 31. In this case, even a small damage due to the reactive ion etching is remained in the surface of the silicon substrate 31, OSF (Oxidation-induced Stacking Fault) is liable to occur during the local oxidation for forming the thick silicon oxide film 37 serving as the field oxidation.
It is possible to remove any etching damage during the reactive ion etching prior to the formation of the spacer 36, but in practice, it is rather difficult to remove all etching damages prior to the formation of the silicon nitride film 35. If the spacer 36 having a large stress is formed on the surface in which etching damages are remained, the damages are increased or enhanced during the local oxidation process, so that there might be produced a very large leak current between adjacent elements.
In order to reduce the power consumption of LSI, it is desired to form C-MOB PETs. In this case, in a surface of a silicon substrate, there are formed a P-type well and an N-type well side by side. These wells are often called twin wells. In such wells of low impurity density, when contamination substances are existent, troubles might occur during high temperature process, long time diffusion process and oxidation process. There are various kinds of contamination substances such as substances due to diffusion carrier gas, water and mist of spin drying, particles and organic substances such as resist remaining on a wafer surface.
In N-type well and P-type well, there might be produced etch pits due to Secco-etching, so that a leak current at a junction might be increased or a leak current via the field oxide film between adjacent elements might be increased.
In recent C-MOS devices, characteristics such as BV.sub.ox, Q.sub.BD and ESD relating to a property of a gate oxide film are deteriorated as process trouble.
In order to solve the above mentioned problems, there has been proposed a gettering method.
FIGS. 3a to 3d are schematic cross sectional views showing successive steps of a known method of manufacturing the twin wells.
At first, on a rear surface of a silicon substrate 41 is formed a damage film 42 for collecting contamination substances as shown in FIG. 3a. The damage film 42 is formed at a time of manufacturing a silicon wafer. After forming a silicon oxide film 43 having a thickness of about 1000 .ANG. on a front surface of the silicon substrate 41, a resist 44 is selectively formed as shown in FIG. 3b, and 31p+ N-type impurity ions are implanted into the silicon substrate 41 while the resist 44 is used as a mask. Then, the implanted impurity ions are driven into a bulk of the silicon substrate 41 to form an N-type well 45 as depicted in FIG. 3c. After forming a resist 46 above the N-type well 45, .sup.11 B.sup.+ P-type impurity ions are implanted. Next, the thus implanted P-type impurity ions are driven into the bulk of the silicon substrate 41 to form a P-type well 47 and at the same time a silicon oxide film 48 is formed as shown in FIG. 3d.
As explained above, the damage film 42 is formed on the rear surface of silicon substrate 41 and a part of contamination substances contained in the silicon substrate are moved toward the damage film by performing the gettering treatment using PoCl.sub.3. The remaining contamination substances within the silicon substrate 41 are moved into a boundary surface between the silicon substrate 41 and the silicon oxide film 43. Therefore, by removing the silicon oxide film 43 by performing an etching process using a fluoric acid, the contamination substances can be removed.
After that, a LOCOS field oxide film is formed at a boundary surface between the N-type well 45 and the P-type well 47, gate electrodes are formed via gate oxide films on these wells, lightly doped source and drain regions are formed by using the gate electrodes as masks, side walls are formed on sides of the gate electrodes and highly doped source and drain regions are formed by using the gate electrodes and side walls as masks.
In the known method illustrated in FIGS. 3a to 3d, a small amount of contamination substances collected in the boundary surface between the silicon substrate 41 and the silicon oxide film 43 can be removed only to a limited extent, so that its gettering function is not sufficient. In general, contamination substances within the silicon substrate 41 are liable to be collected in the damage film 42 formed on the rear surface of the silicon substrate 41. However, it is impossible to form such a damage film on the front surface of the silicon substrate, because then it is quite impossible to form a transistor structure at all.
In intrinsic getter, a damage layer is formed within a silicon substrate by implanting ions into the silicon substrate, and contamination substances are collected into this damage layer to improve the device performances. However, such an intrinsic getter could not remove the contamination substances sufficiently, and thus the surfaces of the wells 45 and 47 formed in the front surface of the silicon substrate 41 are liable to be subjected to the damage due to the contamination substances and a transistor leak current becomes large.
Moreover, in the known method of manufacturing the twin-well, a photomask process for forming the N-type well and a photomask process for forming the P-type well are carried out separately, so that these wells could not be formed in a self alignment manner and could not be formed to have a high accuracy in dimension. It is apparent that the number of processes is large and the manufacturing cost is liable to be high.